Electric selecting matrix



ELECTRIC SELECTING MATRIX Filed Nov. 50, 1949 2 SHEETS--SHEET 2 lfm/entera:

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Patented Nov. 20, 19.51

ELECTRIC SELECTING MATRIX George W. Hobbs, Scotia, N. Y., assignor to General Electric Company, a corporation of New York Application November 30, 1949, Serial No. 130,144

8 Claims. l This invention relates to electric selecting matrices and more particularly to a flat-coded kelectric selecting matrix.

Selecting matrices are of considerable use in digital calculating devices as Well as in other systems in which multiple control of electric circuits is required. Matrices of this type are disclosed, for example, in U. S. Patents 2,428,811 and 2,428,812 to Rajchman.

In conventional selecting matrices, a plurality of input conductors are electrically connected in a predetermined order to a plurality of output conductors by individual resistor units of equal resistance value within restricted resistance tolerance limits. Moreover, where selecting matrices are of the nat-coded type, that is, where the conductors and resistors are of thin substantially linear physical form as is found for example in printed circuits and the like, particular dimculty is experienced in forming resistance units of equal resistance value.

It is an object of this invention to provide a selecting matrix in which the resistor units are more readily and easily formed and in which narrow resistance tolerance difiiculties are avoided as compared to conventional selecting matrices.

A further object is to provide a simple reliable fiat-coded selecting matrix readily adaptable t low cost manufacturing methods.

In general, my invention consists of a ilatcoded selecting matrix comprising a plurality of simple two-family matrices electrically interconnected through common single line resistors tapped to provide segments and sub-segments of equal respective resistance values.

For a complete understanding of my invention reference should be had to the following speciiication and the accompanying drawings.

Figs. 1 and la are respectively plan and bottom views of a four pair input, sixteen conductoroutput, flat-coded selecting matrix illustrative of my invention, Fig. 2 is a diagrammatical View` of the selecting matrix shown in Fig. 1 and Fig. 1a, and Fig. 3 is a diagrammatical view of a two family matrix having thirty-two outputs illustrative of a modication of my invention.

Referring to Figs. 1 and 1a of the drawings, I have shown therein a four pair input, sixteen conductor output Hat-coded selecting matrix I illustrative of my invention. Selecting matrix I comprises a base 2 of any suitable insulation material such as steatite or plastic sheet having Ilat sides 3 and 4, opposite ends 5 and 6 and an 2 edge 1. On side 3 of base 2 respectively adjacent ends 5 and 6 two two-family matrices 8 and 9 are flat-coded as by printing or other suitable process. The matrices 8 and 9 comprise respectively a plurality of spaced input conductors l0-l3 and |4-Il having terminal means Ina-13a and 14a-Ila supported by said base and a plurality of output conductors I8-22 and 23-21.

The conductors lli-21 are flat-coded by any suitable process such as the conventional silk screen process described in the National Bureau oi Standards Circular 468 to electrically connect the output conductors of each matrix to its associated input conductors in a predetermined relation, as shown in Fig. 1. The paint used in such printing is a mixture of finely divided silver or copper particles with some binder and may be either air-dried or iired according to the fabricators preference. Insulation and protection from moisture and short circuits is provided by covering the printed surface with lacquer or similar material. If desired, the lacquer can be applied in commotion with a mask in order that certain points be left bare. Cross lines can thereafter be over printed with a good conductive bond assured at the required points.

A pair of flat-coded single-line resistors 28 and 29 comprising strips of resistance coating are painted or otherwise formed on the surface 3 of the base 2 adjacent the respective ends 5 and 6 thereof. 'Ihe spaced output conductors |8-22 of matrix 8 are electrically connected to the resistor 28 at points dividing the resistor into a plurality of segments 30 of equal resistance value. The segments 30 are further divided into subsegments 3| of equal resistance value by a plurality of connectors 32 electrically connected t0 the resistor 28 at points substantially equidistant between adjacent of the conductors |8-22. The output conductors 23-21 and a plurality ol connectors 33 are electrically connected to the resistance 29 in a similar manner, the conductors and connectors being spaced to divide the resistor 29 into segments 34 of equal resistance value and subsegments 35 of equal resistance value. The connectors 32 and 33 are through connectors penetrating through the base 2 and supported thereby.

A third two-family matrix 36 having a first and second plurality of interspaced input conw ductors 31-40 and 4|44 and a plurality of spaced output conductors 45-8I is printed or otherwise nat-coded, as described for matrices 2 and 3, on side 4 of base 2, as shown in Fig. 1a. The input conductors 31-40 and 4|-44 are electrically 3 connected to the output conductors IB-l in a predetermined relation, as shown in Fig. 1a as the conductors are printed. As seen in Fig. la the right hand ends or input conductors 3140 are connected respectively to the connectors 32 and the left hand ends of the conductors lI-M are connected respectively to the connectors 33. The output conductors lli-BI terminate at and are electrically connected to a nat-coded single-line resistor 10 formed on side l of the base 2 adjacent edge 1 thereof and are spaced to engage the resistor 10 at points dividing the resistor into a plurality of segments 1I of equal resistance value. A plurality oi spaced output terminals Til-TIB are electrically connected to the resistor 10 at points intermediate of the output conductors -SI, as shown in Fig. la, to divide each of the -segments 1I into subsegments 12 of equal resistance value between each output conductor andits adj acent output terminals.

To show the operation of selective matrix I' attention is referred to Fig. 2 in which a diagrammatical circuit of thematrix l of Fig. 1 is shown. Each of the elements of the matrix I, shown in Fig. l, is given the same character reference in Fig. 2. In considering the operation of the matrix I, as diagrammatically shown in Fig. 2, assume that the input conductors III-I3 and I4-I1 of respective matrices 3 and 9 are electrically connected to the outputs of a four stage binary counter (not shown), an example of which may be found in my copending application Serial No.-

l50,395, flledMarch 18, 1950, for an Electric Computer and assigned to the same assignee as this present application.

Those skilled in the art will understand that when the inputs III-I1 are connected to a. binary counter (not shown), the polarity of the voltages, positive and negative, may be varied on the inputs III-I1 to represent therein the binary equivalents of the decimals -15. For example, assuming the voltage condition of inputs Il and I5 to represent the iirst digit of a binary number, inputs I6 and I1 the second, I0 and II the third and I2 and I3 the fourth digit and further assuming the condition of input I5 positive and' input Il negative, input I1 positive and input I6 negative, input II positive and input I0 negative and input I3 positive and input I2 negative to represent the binary character zero in each pair of inputs and the reverse voltage condition to represent the binary character 1 in each pair of inputs, the following table then shows the relationship of voltages on the inputs III-I1 required for the binary equivalents of the decimals 0-15.

Input Voltage Relation Decimal System Bina Etqniv- Applying to input conductors III-I1 shown in Fig. 2 the voltage polarity relations produced in accordance with the above table by such a device IlO switching in a predetermined order is providedY by the selective matrix I and each or the output terminals TIJ-TI 5 are excited with positive voltage in accordance with the operation of the biliary counter (not shown). For example, assume-that the binary equivalent of the decimal 0 is stored in the binary counter. In this case, the binary equivalent of the decimal 0 being 0000 the voltage relation of input conductors III-I1 as shown in the iirst line of the above table prevails. Thus, input conductors I3, II. l1 and IBare impressed with positive voltage and negative voltage is applied to input conductors'IZ, I0, I6 and I4. 'Ihe voltage relation thus established on input Yconductors I0-I1 causes the particular output terminal T0 to be excited. In considering the operation of the matrix I producing this result it is seen that conductors I3 and II are electrically connected respectively to output conductors 22 and 2I of matrix 8, thus applying a positive voltage to each of the adjacent subsegments 3| of the resistor 28 between the output conductors 2l and 22 of matrix 8. By applying a positive voltage to each of the subsegments 3I of resistor 28 between the conductors 2|l and 22 a positive voltage is applied to input conductor 40 of matrix 36 which in turn applies a positive voltage to output conductors 5I and 59 electrically connected thereto. In a similar manner input conductors I1 and I5 of matrix 9 being positive in accordance with the first line of the above table, a positive voltage is applied to output conductors 48 and 6I) of matrix 36 through input conductor 42 of matrix 36 and subsegments 35 of resistor 29 between the output conductors 24 and 25 of matrix 9 which are respectively electrically connected to the input conductors I1 and I5. Thus adjacent output conductors 59 and 60 of matrix 36 are each impressed with positive voltage which is applied therethrough to the subsegments 12 of the resistor 10 adjacent the output terminal T0 to produce a predetermined positive output voltage thereon indicating the storage of the binary 0000 in the binary counter. It will be noted that under the assumed voltage relation of input conductors I0-I1 corresponding to the decimal 0 none of the remaining terminals TI-TI5 have two positive voltages applied thereto trom adjacent of the conductors 45-6I. Therefore, a positive output voltage of predetermined value is applied only to terminal T0 corresponding to the decimal 0.

In a similar manner, as successive numbers appear in the binary counter, a predetermined output voltage is switched through the selecting matrix I to a particular one of the output terminals T0-TI5 corresponding to the number stored in the binary counter. The above is merely an illustration of the operation of the selecting matrix I as applied to a binary counter. This electrical selecting matrix or network may be characterized as a multiple stage network having two states, the rst including matrices 8 and 9 and the second comprising matrix 36.

It is understood that in application of the selecting matrix I the output terminals Til-TIS are electrically connected to an associated grounded electric circuit to be energized from the terminals Til-TIS and that the negative side of the supply source for the binary counter used to energize the selecting matrix I is also grounded to provide a complete operable circuit. Each of the terminals Til-TIS for example may be connected to a neon tube or other signal deae'raore vice the opposite side of which is grounded so that the associated signal device is energized when a positive voltage of the predetermined value appears on some one of the terminals Til-TIE. The terminals TO-TIB may also be connected to such digital calculating devices as for example electronic counters, registers or connecters, or to a combination of such devices depending upon the particular use.

i Selecting matrices have many other fields of application in addition to digital calculations and conventional selecting matrices may be applied to such applications. However, an important ieature of my invention is the i'act that the switching above described is accomplished with a matrix having only three single line resistors namely, 28, 29 and 10. In conventional matrices, as for example, the matrices disclosed by Dr. Jan Rajchman in his U. S. Patents 2,428,811 and 2,428,812, a considerably greater number of individual resistors is required. For example, in the four pair input i6 output circuit described above a total of 64 individual resistors is required in a conventional matrix. This number has been reduced to a total of 48 individual resistors which corresponds to the total number of subsegments in the selective matrix I described above. Further, by collecting the single resistors into associated groups forming one resistance for each group the total number of single-line resistances in my matrix has beenreduced to 3.

The advantage of reducing the number oi resistors in a :dat-coded matrix lies in the fact that whereas a single-line resistor can be controlled reasonably well for resistivity throughout its length, control oi resistance from one unit resistor to another to produce separate unit resistors of equal resistance value is relatively dimcult.

Therefore by my invention, I have provided an improved simple, reliable, nat-coded selecting matrix more readily adaptable to low cost manufacturing methods.

It should be noted that my invention is not to be limited to the preferred embodiment illustrated by Fig. l as other forms of base may also be used to advantage in certain cases. That is, the base may take any suitable form, as for eX- ample, a cylinder or toroid, and the matrices may be flat-coded on one side only of the base, if desired.

Further, the invention is not to be confined to equal size matrices. For example, in Fig. 3, I have shown in diagrammatical form a two family thirty-two output flat-coded selective matrix 'i3 illustrative of a modification of my invention. In matrix le the sixteen input conductors are numbered Io-Ii to correspond with the outputs T-Tie of the matrix shown in Figs. 1 and 2 as the voltages impressed on Io-Iis may be obtained by connecting the output terminals TO-TIE of the matrix i respectively to the inputs Io-I15 oi the selecting matrix 13. 'I'he thirty-two outputs of matrix 13 are obtained by connecting a plurality of terminals I4-05, the inputs Io-Ils and an additional pair of inputs |06 and- |01 to a single-line resistor |08 in spaced relation therealong, as shown in Fig. 3, to provide subsegments i09 of equal resistance value. Thus, a thirty-two output selecting matrix is formed oi inputs derived from one and two-family matrices as compared to the sixteen output selecting matrix illustrated by Figs. 1 and 2 and derived from the two two-family matrices 8 and 9.

While I have shown and described a particuous to those skilled in the art that various changes and modiiications may be made without departing from my invention in its broaderV aspects and I, therefore, aim in the appended claims to cover all such changes and modifications as fall within the true spirit and scope of my invention.

What I claim as new and desire to secure by Letters Patent of the United States is:

1. A fiat-coded electric selecting matrix comprising a base of insulation material, a plurality of two-family matrices, a plurality of single-line resistor means tapped at spaced points to produce segments and subsegments oi equal respective resistance values, a plurality of output terminals electrically connected to particular ones of said tap points on one of said resistor means. said two-family matrices being electrically interconnected in a predetermined relation through the remainder of said tap points of said one resistor means and tap points of the others oi said resistor means.

2. An electric selecting matrix comprising a base of insulation material, a plurality of twofamily electric matrices secured to said base. a plurality of single-line resistor means fixed to said base, said two-family matrices being electrically connected each to a particular one of said resistor means in a predetermined relation at points along said resistor means dividing each into segments of equal resistance value and subsegments of equal resistance value, an additional single-line resistor means iixed to said base and electrically connected to one of said matrices in a predetermined relation to divide said additional resistor means into additional segments of equal resistance value, and a plurality of output terminals supported by said base and electrically connected to said additional resistor at points thereon dividing each of said additional segments into additional subsegments of equal resistance value.

3. An electric selecting matrix comprising two electric conductor matrices each provided with a plurality of input conductors and a plurality o! output conductors, a continuous resistor for each of said matrices, electric connections between said output conductors of each of said matrices and equally resistance spaced points of its said resistor, a third matrix provided with a plurality of input conductors and a plurality of output conductors, electric connections between alternate input conductors of said third matrix and said resistors, respectively, at midway resistance points between said connections with the output conductors of said rst and second matrices, a third resistor, electric connections between the output conductors of said third matrix and equally resistance spaced points of said third resistor, output terminals connected to said third resistor at midway resistance points between said output conductor connections, and electric connections between the input and output conductors of each of said matrices providing for a voltage of predetermined polarity on any selected one of said terminals in response to selected polarities oi' said input conductors of said first and second matrices.

4. An electric selecting matrix comprising two electric conductor matrices each provided with pairs of input conductors and an odd number of output conductors, a continuous resistor for each of said matrices, electric connections between said output conductors of each of said matrices and equally resistance spaced points of its said re- 7 slstor, a third matrix provided with a plurality of input conductors and a plurality of output conductors, electric connections between alternate input conductors of said third matrix and said Y resistors, respectively, at midway resistance points between said connections with the output conductors of said ilrst and second matrices, a third resistor, electric connections between the output conductors of said third matrix and equally reI= slstance spaced points of said third resistor, output terminals connected to said third resistor at midway resistance points between said output conductor connections, and electric connections between the input and output conductors of each of said matrices providing for a voltage of predetermined value and polarity on any selected one of said terminals in response to selected polarities of each of said pairs of input conductors oi said first and second matrices.

5. A flat-coded electric selecting matrix comprising a base of insulation material having opposite ends and ilat opposite sides, iirst and second two-family matrices flat-coded on one side of said base respectively adjacent opposite ends thereof, and a third two-family matrix fiatcoded on the opposite side of said base, each of said matrices comprising a plurality of spaced input conductors, a plurality of spaced output conductors electrically connected to said input conductors in a predetermined relation, lirst, second and third resistors respectively electrically connecting associated ends of said output conductors of said rst, second and third matrices, said output conductors being spaced to provide in each of said resistors segments of equal resistance value between adjacent output conductors, connections for connecting each of said first and second resistors to particular ones of said input conductors of said third matrix, said input connectors being connected each to the resistance center of a particular one of said segments of said rst and second resistors to provide sub= segments of said resistors of equal resistance value, a plurality of input terminals on said base electrically connected to said input conductors of said first and second matrices and a plurality of output terminals on said base each electrically connected to the resistance center of a particu lar one of said segments of said third resistor of said third matrix to provide subsegments of said third resistor of equa1 resistance value between adjacent ones of said third matrix output conductors.

6. An electric selecting matrix comprising a base of insulation material, a plurality of twofamily matrices flat-coded on said base, each of -said matrices comprising a plurality of input and a plurality of output conductors electrically interconnected in a predetermined relation, said input conductors of one of said matrices being divided into groups of associated input conductors, terminal means supported by said base for ,said inputconductors of said matrices other than of equal resistance value, an additional substantially ilat single=line resistor means iixed to said base, said output conductors of said one matrix being electrically connected to said additional resistor means at points dividing said resistor means into segments of equal resistance value, a plurality of output terminal means on said base for vsaid selecting matrix electrically connected to said additional resistance means at points intermediatevof said last mentioned points and further dividing said additional resistor means into subsections of equal resistance value.

7. An electric selecting matrix comprising a base of insulation material having opposite ends and fiat opposite sides, rst and second twofamily matrices fiat-coded on one side of said base respectively adjacent opposite ends thereof, each of said matrices comprising a plurality of spaced input conductors, terminal means electrically connected to said input conductors, a plurality of spaced output conductors electrically connected to said input conductors in a predetermined relation, a resistor electrically connecting corresponding ends of said output conductors, said output conductors being spaced to provide segments of said resistor oi equal resistance value between adjacent output conductors, and a plurality of connector means on said base each electrically connected to the resistance center of a particular one of said segments to provide sub-segments of said resistor of equal resistance value. each of said connector means extending through said base, a third two-family matrix Hat-coded on the opposite side of said base, said third matrix comprising a ilrst and second plu'- rality of spaced input conductors and a. plurality of spaced output conductors, said first plurality of input conductors being electrically connected in a predetermined relation to said connector means of said rst matrix, said second plurality of input conductors being electrically connected in a predetermined relation to said connector means of said second matrix, said output conductors of said third matrix being electrically connected to particular one of said ilrst and second plurality of input conductors in a predetermined relation, a third resistor electrically interconnecting adjacent ends of said output conductors of said third matrix, said output conductors being spaced to provide segments of said third resistor of equal resistance value between adjacent output conductors, and a plurality of output terminals on said base each electrically connected to the resistance center of a particular one of said last mentioned segments to provide subsegments of saidy third resistor of equal resistance value.

8. A multiple-stage electrical selecting network, each stage comprising one or more separate electrical matrices having input terminals and output terminals, the output terminals of prior stages being connected to the input terminals of the next subsequent stages, eachof said matrices comprising input conductors extending from said input terminals, output conductors suitably respectively directly crossconnected with said input conductors and a single resistor element having a plurality of equally spaced equal resistance taps, alternate ones of said taps being connected to said output conductors and said output terminals whereby simultaneous application of a voltage to two adjacent output conductors causes a similar voltage at the output terminal connected tothe resistor tap intermediate theresistor taps to which said two ad- Number Nlme Date jacent output conductors are connected. 2.428.812 Rajchman Qct. 14. 1947 i GEORGE W. HOBBS. 2,473,444 Rajchman June 14, 1949 REFERENCES CITED 5 m1 COTE; lsEtcERmENCEi it H Digi ompu r w ng C ou s, C. mpg; gwigenrferenceb are of record in the Page, Electronics, September 1948, patg'es4 110-118. D Reemer Networks for Mumposmon switch- UNITED STATES PATENTS ing, Brown and Rochester. Proc. I. R. E.. April Number Name Date lo 1949. Niles 139-147.

2,428,811 Rajchman Oct. 14, 1947 

